赵睿轩,周强,王思琦.基于“选择性缓存处理机制”的FPGA纸病检测系统[J].中国造纸学报,2021,(1):63-70 本文二维码信息
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基于“选择性缓存处理机制”的FPGA纸病检测系统
FPGA Paper Defect Detection System based on "Selective Buffer Processing Mechanism"
投稿时间:2020-01-18  
DOI:10.11981/j.issn.1000-6842.2021.01.63
中文关键词:  纸病检测  FPGA  选择性缓存处理机制  流水线处理
Key Words:paper defect detection  FPGA  selective cache processing mechanism  pipeline processing
基金项目:陕西省科技计划项目(2019GY-090);咸阳市科技计划项目(2017K02-06)。
作者单位E-mail
赵睿轩 陕西科技大学电气与控制工程学院陕西西安710021 709679542@163.com 
周强 陕西科技大学电气与控制工程学院陕西西安710021  
王思琦 陕西科技大学电气与控制工程学院陕西西安710021  
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中文摘要:
      针对纸病检测系统普遍存在的快速性与实时性均较差问题,借鉴人眼视觉中“选择性注意”机制,提出了采用“选择性缓存处理”方法快速提取与检测纸病。系统采用“CCD + FPGA”的模式,利用FPGA流水线并行处理特性对线阵CCD采集到的图像数据流进行预处理与特征提取,并同时缓存纸病区域图像。由于整个处理过程为流水线式并行处理,且仅缓存纸病区域图像,因此极大地提高了纸病提取检测的速度并节约大量的存储空间。结果表明,该方法硬件资源占用率极小,且能快速、准确地提取纸病信息,具有很强的灵活性与实时性,可以满足高速纸机实时检测的需求。
Abstract:
      Aiming at the lack of rapidity and real-time in the paper defect detection system, referring to the "selective attention" mechanism in human vision, a "selective buffer processing" method was proposed for the rapid extraction and detection of paper defect. The system adopted the hardware mode of "CCD + FPGA" and utilized the parallel processing characteristics of FPGA pipeline to preprocess and extract the image data stream collected by linear array CCD, and cache the paper defect area images at the same time. Because the entire processing process was pipelined and parallel processing, and only the paper defect area images were cached, the speed of paper defect extraction and detection was greatly improved and a large amount of storage space was saved. The experimental results showed that this method had a very small hardware resource occupancy rate and could quickly and accurately extract paper defect information. It had strong flexibility and real-time performance and could meet the requirements of high-speed paper machine with real-time detection.
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