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| FPGA Paper Defect Detection System based on "Selective Buffer Processing Mechanism" |
| Received:January 18, 2020 |
| DOI：10.11981/j.issn.1000-6842.2021.01.63 |
| Key Words:paper defect detection;FPGA;selective cache processing mechanism;pipeline processing |
| Fund Project:陕西省科技计划项目（2019GY-090）；咸阳市科技计划项目（2017K02-06）。 |
| Author Name | Affiliation | E-mail | | ZHAO Ruixuan* | College of Electrical & Control Engineering， Shaanxi University of Science and Technology， Xi'an， Shaanxi Province， 710021 | 709679542@163.com | | ZHOU Qiang | College of Electrical & Control Engineering， Shaanxi University of Science and Technology， Xi'an， Shaanxi Province， 710021 | | | WANG Siqi | College of Electrical & Control Engineering， Shaanxi University of Science and Technology， Xi'an， Shaanxi Province， 710021 | |
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| Abstract: |
| Aiming at the lack of rapidity and real-time in the paper defect detection system， referring to the "selective attention" mechanism in human vision， a "selective buffer processing" method was proposed for the rapid extraction and detection of paper defect. The system adopted the hardware mode of "CCD + FPGA" and utilized the parallel processing characteristics of FPGA pipeline to preprocess and extract the image data stream collected by linear array CCD， and cache the paper defect area images at the same time. Because the entire processing process was pipelined and parallel processing， and only the paper defect area images were cached， the speed of paper defect extraction and detection was greatly improved and a large amount of storage space was saved. The experimental results showed that this method had a very small hardware resource occupancy rate and could quickly and accurately extract paper defect information. It had strong flexibility and real-time performance and could meet the requirements of high-speed paper machine with real-time detection. |
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